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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14558B BCD-to-Seven Segment Decoder
The MC14558B decodes 4-bit binary coded decimal data dependent on the state of auxiliary inputs, Enable and RBI, and provides an active-high seven-segment output for a display driver. An auxiliary input truth table is shown, in addition to the BCD to seven-segment truth table, to indicate the functions available with the two auxiliary inputs. Leading Zero blanking is easily obtained with an external flip-flop in time division multiplexed systems displaying most significant decade first. * * * * * * Supply Voltage Range = 3.0 Vdc to 18 Vdc Segment Blanking for All Illegal Input Combinations Lamp Test Function Capability for Suppression of Non-Significant Zeros Lamp Intensity Function Capable of Driving Two Low-power TTL Loads. One Low-power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range
L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
D SUFFIX SOIC CASE 751B
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS* (Voltages referenced to VSS)
Rating Symbol VDD Vin Iin TA PD Tstg DC Supply Voltage Value Unit V V - 0.5 to + 18 Input Voltage, All Inputs - 0.5 to VDD + 0.5 10 - 55 to + 125 500 - 65 to + 150 DC Input Voltage, per Pin Operating Temperature Range Power Dissipation, per Package Storage Temperature Range mAdc
TA = - 55 to 125C for all packages.
PIN ASSIGNMENT
B C ENABLE RBO RBI D A VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD f g a b c d e e d f a g b c
_C
mW
_C
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
DISPLAY
AUXILIARY INPUT TRUTH TABLE
Enable Pin 3 0 0 1 1 1 RBI Pin 5 0 1 1 0 X BCD Input Code X X 0 0 1-9 0 RBO Pin 4 0 1 1 0 1 Function Performed Lamp Test Blank Segments Display Zero Blank Segments 1-9 Displayed 1 2 3 4 5 6 7 8 9
X = Don't Care RBI = Ripple Blanking Input RBO = Ripple Blanking Output
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14558B 1
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance Quiescent Current (Per Package) Vin = 0 or VDD Iout = 0 A Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD Adc pF Adc IT IT = (1.2 A/kHz) f + IDD IT = (2.4 A/kHz) f + IDD IT = (3.6 A/kHz) f + IDD Adc #Noise immunity specified for worst-case input combination. Noise Margin for both "1" and "0" level = 1.0 V min @ VDD = 5.0 V = 2.0 V min @ VDD = 10 V = 2.5 V min @ VDD = 15 V To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 10-3 (CL - 50) VDDf where: IT is in A (per package), CL in pF, VDD in V, and f in kHz is input frequency. ** The formulas given are for the typical characteristics only at 25_C. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
MC14558B 2
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C; see Figure 1)
Characteristic Symbol tTLH Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns VDD 5.0 10 15 5.0 10 15 tPLH 5.0 10 15 tPHL 5.0 10 15 -- -- 780 275 185 1560 550 370 -- -- -- 580 220 145 1160 440 230 ns Min -- -- -- -- -- -- Typ 100 50 40 100 50 40 Max 200 100 80 200 100 80 ns Unit ns Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time tPLH = (1.7 ns/pF) CL + 495 ns tPLH = (0.66 ns/pF) CL + 187 ns tPLH = (0.5 ns/pF) CL + 120 ns Propagation Delay Time tPHL = (1.7 ns/pF) CL + 695 ns tPHL = (0.66 ns/pF) CL + 242 ns tPHL = (0.5 ns/pF) CL + 160 ns * The formulae given are for the typical characteristics only. tTHL ns
TRUTH TABLE
Inputs Enable Pin 3 1 1 1 1 1 1 1 1 1 1 1 0 0 RBI Pin 5 1 X X X X X X X X X 0 0 1 D Pin 6 0 0 0 0 0 0 0 0 1 1 0 X X C Pin 2 0 0 0 0 1 1 1 1 0 0 0 X X B Pin 1 0 0 1 1 0 0 1 1 0 0 0 X X A Pin 7 0 1 0 1 0 1 0 1 0 1 0 X X a Pin 13 1 0 1 1 0 1 0 1 1 1 0 1 0 b Pin 12 1 0 1 1 1 0 0 1 1 1 0 1 0 c Pin 11 1 0 0 1 1 1 1 1 1 1 0 1 0 d Pin 10 1 0 1 1 0 1 1 0 1 0 0 1 0 Outputs* e Pin 9 1 1 1 0 0 0 1 0 1 0 0 1 0 f Pin 15 1 1 0 0 1 1 1 0 1 1 0 1 0 g Pin 14 0 0 1 1 1 1 1 0 1 1 0 1 0 RBO Pin 4 1 1 1 1 1 1 1 1 1 1 0 0 1 Blank Blank Display
* All non-valid BCD input codes produce a blank display. X = Don't Care 20 ns ANY INPUT 10% tPLH 90% 50% tPHL 50% tTLH 90% tTHL 10% 20 ns
ANY OUTPUT
Figure 1. Signal Waveforms
MOTOROLA CMOS LOGIC DATA
MC14558B 3
LOGIC DIAGRAM
a b d e g c RBO 13 12 10 15 f 14 11
9
3
5
7
1
2
ENABLE
RBI
C
6
MC14558B 4
D
A
B
4
MOTOROLA CMOS LOGIC DATA
TYPICAL APPLICATIONS
N4 N3 N2 N1 N-1 N-2 N-3
VSS
RBI
RBO
RBI
RBO
RBI
RBO
RBI
RBO
RBI
RBO
RBI
RBO
RBI
RBO
En LAMP TEST
En
En
En
En
En VSS
En
Figure 2. Leading and Trailing Zero Suppression with Lamp Test
N4
N3
N2
N1 VDD
N-1
N-2
N-3
RBI
RBO
RBI
RBO
RBI
RBO
RBI
RBO
RBI
RBO
RBI
RBO
RBI
RBO
BLANKING
En
En
En
En
En
En
En
Figure 3. Leading and Trailing Zero Suppression with PWM Intensity Blanking and No Lamp Test
N4
N3
N2
N1
N-1
N-2
N-3
RBI
RBO
RBI
RBO
RBI
RBO
RBI
RBO
RBI
RBO
RBI
RBO
RBI
RBO
En
En
En
En
En
En
En
BLANKING LAMP TEST
Figure 4. Zero Suppression with Lamp Test and Intensity Blanking
MOTOROLA CMOS LOGIC DATA
MC14558B 5
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MC14558B 6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MOTOROLA CMOS LOGIC DATA
*MC14558B/D*
MC14558B MC14558B/D 7

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